1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a semiconductor device as well as a method of manufacturing a nonvolatile semiconductor memory device.
2. Description of the Background Art
The nonvolatile semiconductor memory device and the semiconductor device have been miniaturized and downsized. As the nonvolatile semiconductor memory device is miniaturized, the spacing between floating gates is decreased and a capacitance formed between the floating gates adjacent to each other is increased. Therefore, in a read operation, a change in amount of electric charge accumulated in a floating gate adjacent to a floating gate of a selected memory cell causes a similar phenomenon to the phenomenon that occurs in the case where electric charge is injected into the floating gate of the selected memory cell. Accordingly, the threshold voltage of the selected memory cell varies, which results in a problem of difficulty in accurately reading electrical information of the selected memory cell. Further, as the semiconductor device is miniaturized, the spacing between interconnect lines provided in the semiconductor device is decreased and a capacitance between the interconnect lines is increased, which results in a problem that the processing speed of the semiconductor device decreases.
Under the circumstances, various semiconductor devices having a decreased capacitance between interconnect lines have recently been proposed. For example, Japanese Patent Laying-Open No. 2000-353740 discloses a semiconductor device having a semiconductor substrate, a plurality of interconnect lines formed on a main surface of the semiconductor substrate, an insulating film formed on the top surface of the interconnect line and having a larger width than the interconnect line, and an interlayer insulating film formed to cover the interconnect lines each.
In such a semiconductor device, the insulating film formed on the interconnect line forms an overhang, namely projecting edge, which facilitates formation of a gap in the interlayer insulating film in a region between interconnect lines, and accordingly the capacitance formed between the interconnect lines is decreased. Further, Japanese Patent Laying-Open No. 2001-217310 discloses a semiconductor device having a semiconductor substrate, a plurality of interconnect lines formed via a first electrically conductive film on a main surface of the semiconductor substrate, a second electrically conductive film formed on the top surface of the interconnect line and larger in width than the interconnect line, and an interlayer insulating film formed to cover the interconnect lines.
In such a semiconductor device, the second electrically conductive film forms an overhang, a gap is formed in the interlayer insulating film in a region between interconnect lines, and accordingly a capacitance between the interconnect lines is decreased. Furthermore, Japanese Patent Laying-Open No. 2001-085519 discloses a semiconductor device having an interconnect line formed with its width increasing as the upward distance from the top of a main surface of a semiconductor substrate increases and an interlayer insulating film formed to cover the interconnect line.
In this semiconductor device, the top surface of the interconnect line has an overhang as formed and a gap is formed between interconnect lines. The capacitance formed between the interconnect lines is thus decreased.